TY - CHAP U1 - Konferenzveröffentlichung A1 - Freudenberger, Jürgen A1 - Wegmann, Thomas A1 - Spinner, Jens T1 - An efficient hardware implementation of sequential stack decoding of binary block codes T2 - IEEE 5th International Conference on Consumer Electronics - Berlin, (ICCE-Berlin), 6-9 Sept. 2015 N2 - This work proposes an efficient hardware Implementation of sequential stack decoding of binary block codes. The decoder can be applied for soft input decoding for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. KW - sequential decoding KW - BCH codes KW - binary codes KW - block codes KW - concatenated codes Y1 - 2015 SN - 978-1-4799-8748-1 SB - 978-1-4799-8748-1 U6 - https://doi.org/10.1109/ICCE-Berlin.2015.7391215 DO - https://doi.org/10.1109/ICCE-Berlin.2015.7391215 N1 - Volltextzugriff für Hochschulangehörige via Datenbank IEEE Xplore SP - 135 EP - 138 ER -