TY - CHAP A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Shavgulidze, Sergo T1 - Estimation of channel state information for non-volatile flash memories T2 - IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin), 3-6 Sept. 2017, Berlin, Germany N2 - Error correction coding based on soft-input decoding can significantly improve the reliability of flash memories. Such soft-input decoding algorithms require reliability information about the state of the memory cell. This work proposes a channel model for soft-input decoding that considers the asymmetric error characteristic of multi-level cell (MLC) and triple-level cell (TLC) memories. Based on this model, an estimation method for the channel state information is devised which avoids additional pilot data for channel estimation. Furthermore, the proposed method supports page-wise read operations. KW - Channel estimation KW - Decoding KW - Error correction codes KW - Flash memories KW - Integrated circuit reliability Y1 - 2017 SN - 978-1-5090-4015-5 SN - 978-1-5090-4014-8 U6 - http://dx.doi.org/10.1109/ICCE-Berlin.2017.8210594 N1 - Volltextzugriff für Hochschulangehörige via Datenbank IEEE Xplore SP - 69 EP - 73 ER - TY - CHAP A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Shavgulidze, Sergo T1 - A channel and source coding approach for the binary asymmetric channel with applications to MLC flash memories T2 - SCC 2017, 11th International ITG Conference on Systems, Communications and Coding, February 6 – 9, 2017, Hamburg, Germany N2 - The binary asymmetric channel (BAC) is a model for the error characterization of multi-level cell (MLC) flash memories. This contribution presents a joint channel and source coding approach improving the reliability of MLC flash memories. The objective of the data compression algorithm is to reduce the amount of user data such that the redundancy of the error correction coding can be increased in order to improve the reliability of the data storage system. Moreover, data compression can be utilized to exploit the asymmetry of the channel to reduce the error probability. With MLC flash memories data compression has to be performed on block level considering short data blocks. We present a coding scheme suitable for blocks of 1 kilobyte of data. Y1 - 2017 UR - https://ieeexplore.ieee.org/document/7938044 SN - 978-3-8007-4362-9 N1 - Volltextzugriff für Hochschulangehörige via Datenbank IEEE Xplore SP - 1 EP - 6 ER - TY - GEN A1 - Rajab, Mohammed T1 - Error correction for non-volatile memories N2 - Vortrag auf dem Doktorandenkolloquium des Kooperativen Promotionskollegs der HTWG, 09.07.2015 Y1 - 2015 ER - TY - JOUR A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Rohweder, Daniel A1 - Safieh, Malek T1 - A codec architecture for the compression of short data blocks JF - Journal of Circuits, Systems and Computers N2 - This work proposes a lossless data compression algorithm for short data blocks. The proposed compression scheme combines a modified move-to-front algorithm with Huffman coding. This algorithm is applicable in storage systems where the data compression is performed on block level with short block sizes, in particular, in non-volatile memories. For block sizes in the range of 1(Formula presented.)kB, it provides a compression gain comparable to the Lempel–Ziv–Welch algorithm. Moreover, encoder and decoder architectures are proposed that have low memory requirements and provide fast data encoding and decoding. Y1 - 2017 U6 - http://dx.doi.org/10.1142/S0218126618500196 SN - 0218-1266 VL - 27 IS - 2 SP - 1 EP - 17 ER - TY - CHAP A1 - Ahrens, Tobias A1 - Rajab, Mohammed A1 - Freudenberger, Jürgen T1 - Compression of short data blocks to improve the reliability of non-volatile flash memories T2 - International Conference on Information and Digital Technologies (IDT), 5-7 July 2016, Rzeszów, Poland N2 - This work investigates data compression algorithms for applications in non-volatile flash memories. The main goal of the data compression is to minimize the amount of user data such that the redundancy of the error correction coding can be increased and the reliability of the error correction can be improved. A compression algorithm is proposed that combines a modified move-to-front algorithm with Huffman coding. The proposed data compression algorithm has low complexity, but provides a compression gain comparable to the Lempel-Ziv-Welch algorithm. KW - Redundancy KW - Data compression KW - Error correction KW - Flash memories KW - Huffman codes Y1 - 2016 SN - 978-1-4673-8861-0 U6 - http://dx.doi.org/10.1109/DT.2016.7557141 N1 - Volltextzugriff für Angehörige der Hochschule Konstanz via Datenbank IEEE Xplore möglich. SP - 1 EP - 4 PB - IEEE ER - TY - PAT A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Baumhof, Christoph T1 - Methods and Apparatus for Error Correction Coding Based on Data Compression N2 - Embodiments are generally related to the field of channel and source coding of data to be sent over a channel, such as a communication link or a data memory. Some specific embodiments are related to a method of encoding data for transmission over a channel, a corresponding decoding method, a coding device for performing one or both of these methods and a computer program comprising instructions to cause said coding device to perform one or both of said methods. Y1 - 2018 UR - https://patentscope.wipo.int/search/en/detail.jsf?docId=US221774105 ER - TY - CHAP A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Shavgulidze, Sergo T1 - A soft-input bit-flipping decoder for generalized concatenated codes T2 - IEEE International Symposium on Information Theory (ISIT), 17-22 June 2018, Vail, CO, USA N2 - Generalized concatenated (GC) codes with soft-input decoding were recently proposed for error correction in flash memories. This work proposes a soft-input decoder for GC codes that is based on a low-complexity bit-flipping procedure. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-input decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer Reed-Solomon codes, this bit-flipping decoder can improve the decoding performance and reduce the decoding complexity compared to the previously proposed sequential decoding. The bit-flipping decoder achieves a decoding performance similar to a maximum likelihood decoder for the inner codes. Y1 - 2018 UR - https://ieeexplore.ieee.org/document/8437537 U6 - http://dx.doi.org/10.1109/ISIT.2018.8437537 SN - 2157-8117 N1 - Volltextzugriff für Angehörige der Hochschule Konstanz via Datenbank IEEE Xplore möglich. SP - 1301 EP - 1305 ER - TY - JOUR A1 - Rajab, Mohammed A1 - Shavgulidze, Sergo A1 - Freudenberger, Jürgen T1 - Soft-input Bit-flipping Decoding of Generalized Concatenated Codes for Application in Non-volatile Flash Memories JF - IET Communications N2 - Error correction coding based on soft-input decoding can significantly improve the reliability of non-volatile flash memories. This work proposes a soft-input decoder for generalized concatenated (GC) codes. GC codes are well suited for error correction in flash memories for high reliability data storage. We propose GC codes constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. The extended BCH codes enable an efficient hard-input decoding. Furthermore, a low-complexity soft-input decoding method is proposed. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer Reed-Solomon codes, this acceptance criterion can improve the decoding performance and reduce the decoding complexity. The presented simulation results show that the proposed bit-flipping decoder in combination with outer error and erasure decoding can outperform maximum likelihood decoding of the inner codes. Y1 - 2018 UR - https://digital-library.theiet.org/content/journals/10.1049/iet-com.2018.5534 U6 - http://dx.doi.org/10.1049/iet-com.2018.5534 SN - 1751-8636 SP - 1 EP - 8 ER - TY - JOUR A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed A1 - Shavgulidze, Sergo T1 - A Source and Channel Coding Approach for Improving Flash Memory Endurance JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems N2 - The introduction of multiple-level cell (MLC) and triple-level cell (TLC) technologies reduced the reliability of flash memories significantly compared with single-level cell flash. With MLC and TLC flash cells, the error probability varies for the different states. Hence, asymmetric models are required to characterize the flash channel, e.g., the binary asymmetric channel (BAC). This contribution presents a combined channel and source coding approach improving the reliability of MLC and TLC flash memories. With flash memories data compression has to be performed on block level considering short-data blocks. We present a coding scheme suitable for blocks of 1 kB of data. The objective of the data compression algorithm is to reduce the amount of user data such that the redundancy of the error correction coding can be increased in order to improve the reliability of the data storage system. Moreover, data compression can be utilized to exploit the asymmetry of the channel to reduce the error probability. With redundant data, the proposed combined coding scheme results in a significant improvement of the program/erase cycling endurance and the data retention time of flash memories. Y1 - 2018 UR - https://ieeexplore.ieee.org/document/8290563 U6 - http://dx.doi.org/10.1109/TVLSI.2018.2797078 SN - 1557-9999 N1 - Volltextzugriff für Angehörige der Hochschule Konstanz via Datenbank IEEE Xplore möglich. VL - 26 IS - 5 SP - 981 EP - 990 ER - TY - CHAP A1 - Freudenberger, Jürgen A1 - Rajab, Mohammed T1 - Chase decoding for quantized reliability information with applications to flash memories T2 - 3rd Baden-Württemberg Center of Applied Research Symposium on Information and Communication Systems - SInCom 2016 - Karlsruhe, December 2nd, 2016 Y1 - 2016 UR - http://nbn-resolving.de/urn:nbn:de:bsz:ofb1-opus4-17866 SN - 978-3-943301-21-2 SP - 7 EP - 10 ER -