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Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm

  • The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary-based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries.

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Metadaten
Author:Malek Safieh, Jürgen FreudenbergerORCiDGND
URL:https://ieeexplore.ieee.org/document/8805609
DOI:https://doi.org/10.1049/iet-cds.2018.5017
ISSN:1751-8598
Parent Title (English):IET Circuits, Devices & Systems
Volume:13
Document Type:Article
Language:English
Year of Publication:2019
Release Date:2020/01/10
Issue:5
First Page:576
Last Page:583
Note:
Volltextzugriff für Angehörige der Hochschule Konstanz via Datenbank IEEE Xplore möglich.
Institutes:Institut für Systemdynamik - ISD
Relevance:Peer reviewed Publikation in Thomson-Reuters-Listung
Open Access?:Nein
Licence (English):License LogoLizenzbedingungen IEEE