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Universal Memory Automaton and Automated Verilog HDL Code Generation for a Cache Coherency Snooping Protocol

  • This paper introduces the concept of Universal Memory Automata (UMA) and automated compilation of Verilog Hardware Description Language (HDL) code at Register Transfer Level (RTL) from UMA graphs for digital designs. The idea is based on the observation that Push Down Automata (PDA) are able to process the Dyk-Language - commonly known as the balanced bracket problem - with a finite set of states while Finite State Machines (FSM) require an infinite set of states. Since infinite sets of states are not applicable to real designs, PDAs appear promising for types of problems similar to the Dyk-Language. PDAs suffer from the problem that complex memory operations need to be emulated by a specific stack management. The presented UMA therefore extends the PDA by other types of memory, e.g. Queue, RAM or CAM. Memories that are eligible for UMAs are supposed to have at least one read and one write port and a one-cycle read/write latency. With their modified state-transfer- and output-function, UMAs are able to operate user-defined numbers, configurations and types of memories. Proof of concept is given by an implementation of a cache coherency protocol, i.e. a practical problem in microprocessor design.

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Author:Matthias Fertig
Parent Title (English):MPC / Multi-Projekt-Chip-Gruppe Baden-Württemberg : Tagungsband zum Workshop der Multiprojekt-Chip-Gruppe Baden-Württemberg / Hrsg: Hochschule Ulm
Publisher:Hochschule Ulm
Place of publication:Ulm
Document Type:Preprint
Year of Publication:2021
Release Date:2021/09/24
First Page:35
Last Page:42
Volltextzugriff zu den Tagungsbänden unter http://www.mpc-gruppe.de derzeit inaktiv.
Institutes:Fakultät Elektrotechnik und Informationstechnik
Open Access?:Ja
Relevance:Externer wissenschaftlicher Fachvortrag oder Poster
Licence (German):License LogoUrheberrechtlich geschützt