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Bit-Labeling and Page Capacities of TLC Non-Volatile Flash Memories

  • The reliability of flash memories suffers from various error causes. Program/erase cycles, read disturb, and cell to cell interference impact the threshold voltages and cause bit errors during the read process. Hence, error correction is required to ensure reliable data storage. In this work, we investigate the bit-labeling of triple level cell (TLC) memories. This labeling determines the page capacities and the latency of the read process. The page capacity defines the redundancy that is required for error correction coding. Typically, Gray codes are used to encode the cell state such that the codes of adjacent states differ in a single digit. These Gray codes minimize the latency for random access reads but cannot balance the page capacities. Based on measured voltage distributions, we investigate the page capacities and propose a labeling that provides a better rate balancing than Gray labeling.

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Metadaten
Author:Johann-Philipp ThiersORCiD, Daniel Nicolas BailonORCiD, Jürgen FreudenbergerORCiDGND
URL:https://edas.info/p27511
Parent Title (English):ICCE Berlin 2020, 10th IEEE International Conference on Consumer Electronics, 9.-12.11.2020, virtual
Publisher:IEEE
Document Type:Conference Proceeding
Language:English
Year of Publication:2020
Release Date:2021/01/18
Page Number:6
Institutes:Institut für Systemdynamik - ISD
Open Access?:Ja
Relevance:Keine peer reviewed Publikation (Wissenschaftlicher Artikel und Aufsatz, Proceeding, Artikel in Tagungsband)