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Adjusting the friction response of the wheel-rail interface is a key factor in the mitigation of wear and rollingcontact fatigue (RCF) in rails. The use of top-of-rail (TOR) friction conditioners has the potential to reduce maintenance costs significantly. Unfortunately, conflicting results on the use of commercial TOR conditioners have been presented in the literature. In this work, the performance of commercial TOR conditioners and a laboratory-made formulation were tested, both on the lab scale and in field measurements. Friction results are discussed together with the structural and chemical analysis of the tested materials.
Digitale Transformation
(2015)
Strategie der digitalen Ära
(2015)
Karl Bernhard (1859-1937)
(2018)
Ulrich Finsterwalder
(2016)
Wettbewerb und Wagnis
(2015)
This paper introduces the concept of Universal Memory Automata (UMA) and automated compilation of Verilog Hardware Description Language (HDL) code at Register Transfer Level (RTL) from UMA graphs for digital designs. The idea is based on the observation that Push Down Automata (PDA) are able to process the Dyk-Language - commonly known as the balanced bracket problem - with a finite set of states while Finite State Machines (FSM) require an infinite set of states. Since infinite sets of states are not applicable to real designs, PDAs appear promising for types of problems similar to the Dyk-Language. PDAs suffer from the problem that complex memory operations need to be emulated by a specific stack management. The presented UMA therefore extends the PDA by other types of memory, e.g. Queue, RAM or CAM. Memories that are eligible for UMAs are supposed to have at least one read and one write port and a one-cycle read/write latency. With their modified state-transfer- and output-function, UMAs are able to operate user-defined numbers, configurations and types of memories. Proof of concept is given by an implementation of a cache coherency protocol, i.e. a practical problem in microprocessor design.
Generative Design Software - How does digitalization change the professional profile of architects
(2019)
Abstract, Poster und Vortrag
Das hier beschriebene und auf einem FPGA vom Typ Spartan-3A DSP realisierte System dient dazu, auf besonders effiziente Weise die Häufigkeitsverteilung nicht erkannter fehlerhafter Nachrichten mit verschiedenen CRCPolynomen
zu berechnen. Damit die Berechnung in möglichst kurzer Zeit stattfindet, wurde das System aus 64 parallel arbeitenden Instanzen von CRC-Findern in mehrstufiger Fließbandorganisation aufgebaut. In der hier beschriebenen Ausbaustufe erreicht das System eine Gesamtleistung von 6,4 ·109 Operationen in der Sekunde.
Ingenieure auf die Bühne
(2018)
Steps to the stage
(2017)