Refine
Document Type
- Article (4) (remove)
Has Fulltext
- no (4)
Keywords
- Block codes (1)
- CONCATENATED codes (1)
- CONVOLUTION codes (1)
- Concatenated codes (1)
- Decoding (1)
- ERROR-correcting codes (1)
- REED-Solomon codes (1)
- TURBO codes (1)
Institute
Flash-Speicher wurden ursprünglich als Speichermedium für Digitalkameras entwickelt, finden inzwischen aber in vielen Bereichen Anwendung.
Die in Konstanz ansässige Firma Hyperstone GmbH ist ein führender Anbieter von Flashcontrollern für Anwendungen mit erhöhten Anforderungen an Zuverlässigkeit und Datenintegrität. Bereits seit April 2011 kooperiert die Firma Hyperstone mit der HTWG Konstanz bei der Entwicklung von Fehlerkorrekturverfahren für einen zuverlässigen Einsatz von Flash-Speichern. Aufgrund der rasanten Entwicklung bei Flashspeicherbausteinen ist auch eine stetige Weiterentwicklung der Korrekturverfahren notwendig. Im Rahmen dieser Kooperation wurde inzwischen zwei Flashcontroller mit sehr leistungsfähiger Fehlerkorrektur entwickelt. Der folgende Artikel gibt Einblick in den Einsatz von Flash-Speichern und erläutert die Notwendigkeit für eine leistungsfähige Fehlerkorrektur.
This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose-Chaudhuri-Hocquenghem (BCH) and outer Reed-Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.
This paper proposes a soft input decoding algorithm and a decoder architecture for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In this paper, a representation of the block codes based on the trellises of supercodes is proposed in order to reduce the memory requirements for the representation of the BCH codes. This enables an efficient hardware implementation. The results for the decoding performance of the overall GC code are presented. Furthermore, a hardware architecture of the GC decoder is proposed. The proposed decoder is well suited for applications that require very low residual error rates.
Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.