Refine
Year of publication
Document Type
- Conference Proceeding (46)
- Article (30)
- Patent (3)
Keywords
- Antenna arrays (1)
- BCH codes (1)
- Binary codes (1)
- Block codes (2)
- CONCATENATED codes (1)
- CONVOLUTION codes (1)
- Capacity (1)
- Channel capacity (1)
- Channel coding (1)
- Channel estimation (3)
- Channel fading (1)
- Code-based cryptography (1)
- Code-based cryptosystem (1)
- Coded modulation (1)
- Codes over Gaussian integers (1)
- Computational complexity (2)
- Computer Science Applications (1)
- Concatenated codes (3)
- Data compression (2)
- Data retention time (1)
- Decoding (3)
- Decoding attack (1)
- Digital arithmetic (1)
- Digital modulation (1)
- ERROR-correcting codes (1)
- Electrical and Electronic Engineering (1)
- Elliptic curve cryptography (2)
- Elliptic curve point multiplication (2)
- Encoding (1)
- Error correction (1)
- Error correction codes (3)
- Error correction coding (1)
- Flash memories (3)
- Gaussian integers (3)
- Gaussian processes (1)
- Generalized concatenated codes (1)
- Generalized multi-stream spatial modulation (1)
- Generalized multistream spatial modulation (1)
- Hardware and Architecture (1)
- Huffman codes (1)
- Human-Computer Interaction (1)
- Hurwitz integers (1)
- Index modulation (IM) (1)
- Information theory (1)
- Information-set decoding (1)
- Integrated circuit reliability (1)
- Lattices (2)
- Low-complexity detection (2)
- MEMS microphones (1)
- MIMO (1)
- MVDR beamforming (1)
- Machine learning (1)
- Maximum likelihood decoding (1)
- Maximum-likelihood detection (1)
- McEliece cryptosystem (3)
- Mont-gomery modular reduction (1)
- Montgomery modular multiplication (1)
- Montgomery modular reduction (1)
- Multichannel Wiener filter (1)
- Multiple-input/multiple-output (MIMO) (1)
- Multistage detection (2)
- Neural network (1)
- Niederreiter cryptosystem (1)
- Non-volatile NAND flash (1)
- Non-volatile memory (1)
- Nonvolatile NAND flash (1)
- One Mannheim error correcting codes (OMEC) (1)
- Point multiplication (1)
- Polar codes (1)
- Processor (1)
- Program/erase cycles (1)
- Public key cryptography (2)
- Public-key cryptography (4)
- REED-Solomon codes (1)
- Read reference adjustment (1)
- Redundancy (2)
- Reed-Muller (RM) codes (1)
- Resource-constrained systems (1)
- Restricted error values (1)
- Signal constellations (2)
- Signal detection (1)
- Solinas primes (1)
- Spatial modulation (3)
- Spatial modulation (SM) (1)
- Spatial permutation modulation (SPM) (1)
- Speech signal processing (1)
- Sprachakustik (1)
- Sprachverarbeitung (1)
- TURBO codes (1)
- Threshold calibration (1)
- Wind noise reduction (1)
- algebraic codes (1)
- binary codes (1)
- block codes (1)
- concatenated codes (2)
- maximum distance separable codes (1)
- modulation coding (1)
- sequential decoding (1)
Institute
The binary asymmetric channel (BAC) is a model for the error characterization of multi-level cell (MLC) flash memories. This contribution presents a joint channel and source coding approach improving the reliability of MLC flash memories. The objective of the data compression algorithm is to reduce the amount of user data such that the redundancy of the error correction coding can be increased in order to improve the reliability of the data storage system. Moreover, data compression can be utilized to exploit the asymmetry of the channel to reduce the error probability. With MLC flash memories data compression has to be performed on block level considering short data blocks. We present a coding scheme suitable for blocks of 1 kilobyte of data.
This work proposes a lossless data compression algorithm for short data blocks. The proposed compression scheme combines a modified move-to-front algorithm with Huffman coding. This algorithm is applicable in storage systems where the data compression is performed on block level with short block sizes, in particular, in non-volatile memories. For block sizes in the range of 1(Formula presented.)kB, it provides a compression gain comparable to the Lempel–Ziv–Welch algorithm. Moreover, encoder and decoder architectures are proposed that have low memory requirements and provide fast data encoding and decoding.
This work presents a new concept to implement the elliptic curve point multiplication (PM). This computation is based on a new modular arithmetic over Gaussian integer fields. Gaussian integers are a subset of the complex numbers such that the real and imaginary parts are integers. Since Gaussian integer fields are isomorphic to prime fields, this arithmetic is suitable for many elliptic curves. Representing the key by a Gaussian integer expansion is beneficial to reduce the computational complexity and the memory requirements of secure hardware implementations, which are robust against attacks. Furthermore, an area-efficient coprocessor design is proposed with an arithmetic unit that enables Montgomery modular arithmetic over Gaussian integers. The proposed architecture and the new arithmetic provide high flexibility, i.e., binary and non-binary key expansions as well as protected and unprotected PM calculations are supported. The proposed coprocessor is a competitive solution for a compact ECC processor suitable for applications in small embedded systems.
This contribution presents a data compression scheme for applications in non-volatile flash memories. The objective of the data compression algorithm is to reduce the amount of user data such that the redundancy of the error correction coding can be increased in order to improve the reliability of the data storage system. The data compression is performed on block level considering data blocks of 1 kilobyte. We present an encoder architecture that has low memory requirements and provides a fast data encoding.
Large-scale quantum computers threaten the security of today's public-key cryptography. The McEliece cryptosystem is one of the most promising candidates for post-quantum cryptography. However, the McEliece system has the drawback of large key sizes for the public key. Similar to other public-key cryptosystems, the McEliece system has a comparably high computational complexity. Embedded devices often lack the required computational resources to compute those systems with sufficiently low latency. Hence, those systems require hardware acceleration. Lately, a generalized concatenated code construction was proposed together with a restrictive channel model, which allows for much smaller public keys for comparable security levels. In this work, we propose a hardware decoder suitable for a McEliece system based on these generalized concatenated codes. The results show that those systems are suitable for resource-constrained embedded devices.
This work proposes a decoder implementation for high-rate generalized concatenated (GC) codes. The proposed codes are well suited for error correction in flash memories for high reliability data storage. The GC codes are constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. The extended BCH codes enable high-rate GC codes. Moreover, the decoder can take advantage of soft information. For the first three levels of inner codes we propose an optional Chase soft decoder. In this work, the code construction is explained and a decoder architecture is presented. Furthermore, area and throughput results are discussed.
Error correction coding (ECC) for optical communication and persistent storage systems require high rate codes that enable high data throughput and low residual errors. Recently, different concatenated coding schemes were proposed that are based on binary Bose-Chaudhuri-Hocquenghem (BCH) codes that have low error correcting capabilities. Commonly, hardware implementations for BCH decoding are based on the Berlekamp-Massey algorithm (BMA). However, for single, double, and triple error correcting BCH codes, Peterson's algorithm can be more efficient than the BMA. The known hardware architectures of Peterson's algorithm require Galois field inversion. This inversion dominates the hardware complexity and limits the decoding speed. This work proposes an inversion-less version of Peterson's algorithm. Moreover, a decoding architecture is presented that is faster than decoders that employ inversion or the fully parallel BMA at a comparable circuit size.
The McEliece cryptosystem is a promising candidate for post-quantum public-key encryption. In this work, we propose q-ary codes over Gaussian integers for the McEliece system and a new channel model. With this one Mannheim error channel, errors are limited to weight one. We investigate the channel capacity of this channel and discuss its relation to the McEliece system. The proposed codes are based on a simple product code construction and have a low complexity decoding algorithm. For the one Mannheim error channel, these codes achieve a higher error correction capability than maximum distance separable codes with bounded minimum distance decoding. This improves the work factor regarding decoding attacks based on information-set decoding.
This paper proposes a soft input decoding algorithm and a decoder architecture for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In this paper, a representation of the block codes based on the trellises of supercodes is proposed in order to reduce the memory requirements for the representation of the BCH codes. This enables an efficient hardware implementation. The results for the decoding performance of the overall GC code are presented. Furthermore, a hardware architecture of the GC decoder is proposed. The proposed decoder is well suited for applications that require very low residual error rates.